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Portable, VID Programmed Single Phase Power Supply Controller
POWER MANAGEMENT Description
The SC453 IC is a single chip high-performance Hysteretic PWM controller. With its integrated SmartDriverTM, it powers advanced graphics and core processors. It provides sleep mode and boot voltage support. Automatic "powersave" is present to prevent negative current flow in the low-side FET during light loading conditions saving even more power. The high side driver initially turns on with a weak drive to reduce ringing, EMI, and capacitive turn-on of the low side. A 6-bit DAC, accurate to 0.85%, sets the output voltage reference, and implements the 0.700V to 1.708V range required by the processor. The hysteretic converter uses a comparator without an error amplifier, and therefore provides the fastest possible transient response, while avoiding the stability issues inherent to classical PWM controllers. The DAC is externally slew rate limited to minimize transient currents and audible noise. The SC453 operates from 5VDC and also features softstart, an open-drain PWRGD signal with power good blanking, and an enable input. Programmable current limiting shuts down the SC453 after 32 current limit pulses.
SC453
Features
High Speed Hysteretic Controller Single Phase Operation Selectable Analog or VID Controlled Sleep Setting 6 Bit VID programmable Output Integrated Drivers with Soft-High Side Turn-On Programmable Soft-Start Programmable Boot Voltage Programmable Sleep Voltage with Sleep Mode Under-Voltage Lockout on VCCA Over-voltage Protection on CORE Current Limit Protection on CORE Thermal Protection Power Good Flag with Blanking During VCORE Changes Automatic Power Save at Light Load TSSOP-28 Package
Applications
Low Power Notebook and Laptop Computers Embedded Applications PowerStep IVTM and Smart DriverTM are trademarks of Semtech Corporation.
Typical Application Circuit
V5 VCCA
VCORE 0.700V-1.708V
VIN
Smart Driver
PWM Controller
SC453 Single Phase Power Supply
VID (5:0)
VID Logic and DAC
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R1 R2 0 2 1 C6 1uF 1 1 1 1 1 DRN 8 7 6 5 10uF 10uF 10uF 10uF 1 2 C2 C3 C4 C5 2 2 2 2 2 C7 10uF BST_L 2 10 MBR0530 2 1 1uF
C1 D1
1
Q1
8 7 6 5
D D
3 2 1
SLP 4 SLP 1 1 R6 1.8K 2 SLPV BOOTV PG# HY S 2 C11 270pF DNP 1 1 1 330pF 1nF R10 C12 C13 VID5 1 VID4 VID3 R12 12 VID2 VID1 2 VID0 C21 15nF 1 1 1 1 2 1nF 330pF DNP SS 15 C23 C22 SS 2 2 R13 PG_DEL 16 332 CORE 13 14 17 CORE 1 2 DAC 18 DAC GND 19 REFIN 20 VCCA 21 2 2 2 VCCA CLRF 22 1 R8 2 1.8K CLRF CMP 23 1 R7 2 931 CMP CL 24 CL EN 1uF 5 6 7 8 25
EN
PG#
SLPV
C10
1
2
BOOTV
1nF
PG#
3 2 1
1
54.9K 9 10 11
33.2K
36.5K
VID5
VID5
5 L1 1 3 0.5uH
C15 1 4.7uF 2 + 330uF 1 C18 + 8 7 6 5 8 7 6 5 2
1
1
VID4
VID4
2
Q3 +VCORE
IRF7832 4
Q4
D
VID2
VID2
D
VID1
VID1
4
2
IRF7832
D2 MBRS140L 1 3 2 1 3 2 1 1
R11 0
VID0
VID0
2
PG_DEL
PG_DEL
2
(c) 2006 Semtech Corp.
2
+5V
POWER MANAGEMENT Reference Design
+V_IN
C8 1 10uF
2
EN
Q2
1 DRN 2 TG 4 2 C9 IRF7821 IRF7821 4 BST BG 3 26
TG 27
U1
BG
V5
28
BST
SLP
SC453
PGND
2
1
R3
2
2
R4
1
1
R5
2
HY S
1
R9 4 2 6 CSH 2 C14 0.001
2 C16 + 330uF C17 + 330uF
+VCORE
VID3
VID3
330uF
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SC453
SC453
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltages Input and Output Voltages EN BST to PGND BST to PGND BST to DRN DRN to PGND DRN to PGND TG PGND to AGND Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Lead Temperature (Soldering) 10s Peak IR Reflow Temperature 10 - 40s
Symbol VCCA, V5
VSLPV, V SLP, V VID [0.5], V DAC, V REFIN, V CMP, V HYS, V CORE, V CL, V CLRF, V PG#, V BOOTV, V SS, V GND, V BG, V CLSET
Conditions
Min -0.3 -0.3
Max 7 VCCA +0.3 7
Units V V V V V V V V V V C/W C/W C C
VEN Static Transicent < 100ns -0.3 Static Transient < 100ns TSTG -2 -5 -2 -0.3 JA JC TLEAD TPKG TSSOP-28 TSSOP-28 TSSOP-28 TSSOP-28 -0.3
36 40 7 30 34 BST +0.3 0.3 70 20 300 260
NOTES: (1) Calculated from package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB. (2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Unless otherwise specified: VIN = 15V, VCCA = 5V, and V5 = 5V.
Parameter Supply (VIN, VCCA, V5) VIN Supply Voltage Range V5 Supply Voltage Range VCCA Voltage Range VCCA Quiescent Current
(c) 2006 Semtech Corp.
Symbol
Conditions
Min
Typ
Max
Units
VIN V5 VCCA ICCQ EN is low EN is high in UVLO
3
3.0 4.3 4.5 5.0 5.0
25 6.0 6.0 10 400
V V V A A
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SC453
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter VCCA Operating Current Symbol ICC Conditions Min Typ 5 Max Units mA
Under-Voltage Lockout Circuits (VCCA, V5) Threshold (VCCA falling) VCCA Hysteresis Threshold (V5 falling) V5 Hysteresis VHCCA VHYST CCA VHV5 VHYST V5 3.85 3.47 3.70 190 4.00 210 4.25 3.93 V mV V mV
Fixed Over-Voltage Protection (CORE) Threshold (CORE Rising) Enable Input (EN) Input High Input Low ViH (EN) ViL (EN) 2 0.8 V V VTH CORE
FIXED
1.95
2.00
2.05
V
VCORE Power Good Generator (PG_DEL, PG#)
VDAC = 0.6 - 1.75V Upper Threshold Lower Threshold 1.1x VDAC 0.86x VDAC 1 0.4 0.95x VPULL-UP 0.95x VPULL-UP 0.95x VPULL-UP 0.4 0.8 1007 Clocks 1.15x VDAC 0.9x VDAC
Core Input Threshold
VTH CORE
Note: during UVLO, the output level of this signal is undefined
V
Hysteresis VCORE = VDAC
%
PG# Output Voltage
VPG#
Pulled up with external 680 resistor to VPULL-UP
Either VCORE < 0.88*VDAC, or, VCORE > 1.12*VDAC EN is low or EN is high but UVLO condition
V
VCORE = VDAC pulled-up with external 680 resistor to VPULL-UP 1.2V
PG_DEL Output Voltage
VPG_DEL
Either VCORE < 0.88*VDAC, or, VCORE > 1.12*VDAC EN is low or EN is high but UVLO condition
V
PG_DEL Delay (at start-up)
Measured from PG# assertion
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SC453
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Symbol Conditions Min Typ Max Units
Soft-Start & DAC Slew (SS) Soft-Start/DAC Slew Current
Note: SS cap is not discharged until EN goes low or UVLO cuts in. To enable the converter, SS has to drop below VSS_EN.
Discharge (sink) Current Soft-Start transition 0 < TA < 85C, - 40 < TA < 85 C ISS Sleep Exit, 0 < TA < 85C Sleep Exit, -40 < TA < 85C VID Transition, 0 < TA < 85C VID Transition, -40 < TA < 85C VSS_EN
5 7.5 204 180 102 90
10 10.5 256 240 128 120 40 16 310 320 155 160 100
mA
A
Soft-Start Enable Threshold DAC (VID [5:0]) VID Input Threshold
mV
ViH_VID ViL_VID
0.55 0.45 0 < TA < 85C, VID [5:0] = 000000 "111111(1.708V" 0.812V) -25C < TA < 85C, VID [5:0] = 000000 "111111 (1.708V" 0.700V) -0.85 -2.0 +0.85 +2.0
V
DAC Output Voltage Accuracy Boot Voltage (BOOTV) Input Voltage Offset BOOT Delay Time(1) Sleep (SLP, SLPV) Input Voltage Offset SLP Logic Threshold
% %
VDAC_ERR
VBOOTVVDAC TBOOT
BOOTV = 1.2V 10 35
|3|
% s
VSLPV-VDAC ViH_SLP ViL_SLP
SLPV = 0.8V 2
|3|
% V
0.8
CORE Comparator (CMP, REFIN, HYS) Input Bias Current Input Voltage Offset IREFIN VCMP VREFIN VREFIN = 1.3V |1.5| |2| |3| A mV
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SC453
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Symbol Conditions Min Typ Max Units
CORE Comparator (CMP, REFIN, HYS) (Cont.) RHYS = 17K Hysteresis Setting Current SLP = low ICMP RHYS = 170K VCMP < VREFIN VCMP > VREFIN VCMP < VREFIN VCMP > VREFIN VCMP < VREFIN VCMP > VREFIN -110 90 -7 7 -83 63 -100 100 -10 10 -73 73 -90 110 A -13 13 -63 A 83
Hysteresis Setting Current SLP = high
ISLP_ ICMP
RHYS = 17K
Current Limit Comparator (CL, CLRF, HYS) Input Bias Current Input Voltage Offset ICL VCL- VCLRF RHYS = 17K Current Limit Setting Current SLP = low ICLRF RHYS = 170K VCL < VCLRF VCL > VCLRF VCL < VCLRF VCL > VCLRF VCL < VCLRF VCL > VCLRF 150 250 15 25 120 195 VCL1, 2 = 1.3V |3| 200 300 20 30 150 230 |2| |5| 250 350 A 25 35 180 A 265 A mV
Current Limit Setting Current SLP = high
ISLP_CLRF
RHYS = 17K
Zero-Crossing (Powersave) Comparators (CL, CORE) Offset High Side Driver (TG) Peak Output Current(1) Ipkh RSRC_TG RSINK_TG Rise Time(1) Fall Time(1) trTG tfTG I = 100mA, VBST-VDRN = 5V VDRN < 1V VDRN > 1V 1.5 4.2 1 0.7 60 36 4 1.4 ns ns A VCL- VCORE |5| mV
Output Resistance
I = 100mA, VBST-VDRN = 5V CTG = 3nF, VBST-VDRN = 5V CTG = 3nF, VBST-VDRN = 5V
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SC453
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter High Side Driver (Cont.) Propagation Delay TG Going High(1) Propagation Delay TG Going Low(1) Shoot-thru Protection Delay Time(1) Low Side Driver (BG) Peak Output Current(1) Output Resistance Ipkl RSRC_BG RSINK_BG Rise Time(1) Fall Time(1) Propagation Delay TG Going High(1) Propagation Delay TG Going Low(1)
Notes: 1) Guaranteed by design.
Symbol
Conditions
Min
Typ
Max
Units
tpdhTG tpdlTG tspd
CMP crossing REFIN to 10% point of TG, CTG = 3nF, BG = 0V CMP crossing REFIN to 90% point of TG, CTG = 3nF 21
45 45 30 39
ns ns ns
3 1.0 I = 100mA, V5 = 5V 0.5 CBG = 3nF, V5 = 5V CTG = 3nF, V = 5V CMP crossing REFIN to 10% point of BG, CBG = 3nF, DRN = 0V CMP crossing REFIN to 90% point of TG, CTG = 3nF, DRN = 0V 25 15 35 35 1.2 2.6
A
trBG tfBG tpdhBG tpdlBG
ns ns ns ns
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SC453
POWER MANAGEMENT
Pin Configuration
TOP VIEW
DRN TG BST SLP SLPV BOOTV PG# HYS VID5 VID4 VID3 VID2 VID1 VID0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V5 BG PGND EN CL CMP CLRF VCCA REFIN GND DAC CORE PG_DEL SS
Ordering Information
Device SC453TSTRT SC453EVB
Notes: 1. Only available in tape and reel packaging. A reel contains 2500 devices. 2. Lead-free package compliant with J-STD-020B. Qualified to support maximum IR reflow temperature of 260C for 30 seconds. 3. This device is ESD sensitive. Use of standard ESD handling precautions is required. 4. All parameters subject to change without notice. 5. Lead-free product. This product is fully WEEE and RoHS compliant.
Package TSSOP-28
Temp Range(TJ) -40C to + 125C
EVALUATION BOARD
(28 Pin TSSOP)
Pin Descriptions
Pin# 1 2 3 4 5 6 7 8 9 10 Pin Name DRN TG BST SLP SLPV BOOTV PG# HYS VID5 VID4 Pin Function This pin connects to the junction of the switching and synchronous MOSFETs. Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. Sleep logic input signal. Connect this pin to VCCA to select "VID Sleep Mode". Otherwise, "SLPV Sleep Mode" is selected and the voltage on this pin sets the DAC output during sleep. The voltage on this pin sets the BOOT-Up voltage. Start clock indicator - open drain output. Active low. Core Comparator Hysteresis. Connect to ground thru an external resistor called RHYS. Hysteresis current is established by an internal VREF voltage, 1.7V, divided by RHYS. VID most significant bit main controller voltage programming DAC input. VID input.
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SC453
POWER MANAGEMENT Pin Configuration(Cont.) Descriptions
Pin# 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name VID3 VID2 VID1 VID0 SS PG_DEL CORE DAC GND REFIN VCCA CLRF CMP CL EN PGND BG V5 Pin Function VID input. VID input. VID input. VID least significant bit main controller voltage programming DAC input. Soft-start. An external cap defines the soft-start ramp. Delayed power good - open drain output. When the Main Converter Output approaches and stays within 14% of the VID_DAC setting, and the tCPU_PWRGD period has terminated. This signal is pulled high by an external resistor. Main CORE converter output feedback to the power good generator. A small RC filter should be used to filter out any HF component to prevent faulty trip condition. Main controller digital-to-analog output. Analog ground. Core Comparator reference input pin. Connect to DAC. 5V supply for precision analog circuitry. Current limit reference input pin Core Comparator input pin. Current limit input pin. Enable - active high. This is capable of accepting a 5.0V signal level. Power ground. Connect to the synchronous FET power ground. Output drive for the synchronous (low-side) FET. 5VDC supply for the driver. A capacitor should be connected from V5 to GND.
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SC453
POWER MANAGEMENT Block Diagram

SLPV BOOTV
SLP
VID/SLPV Sleep Mode Detect
REFIN
PG#
PG_DEL
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SC453
POWER MANAGEMENT Applications Information (Cont.)
SUPPLY, BIAS, UVLO, POWER GOOD GENERATOR Supply The chip is optimized to operate from a 5V 5% rail but also designed to work up to 6V maximum supply voltage. Under-Voltage Lock-Out Circuit The Under-Voltage Lock-Out Circuit consists of comparators which monitor the VCCA and V5 voltage levels. The SC453 is in UVLO mode while either supply has not ramped above the upper threshold or has dropped below the lower threshold. During UVLO, the external FETs are held off, tri-stating the output (DRN). Over-Voltage Protection If the CORE voltage is greater than +14% of the DAC (i.e., out of the power good window), the SC453 will latch off and hold the low-side driver on permanently. Either the power or EN must be recycled to clear the latch. The latch is disabled during soft-start and VID/Sleep transitions. For safety, the latch is enabled if the CORE voltage exceeds 2V even during VID/Sleep transitions. Thermal Shutdown The device will be disabled and latched off when the internal junction temperature reaches approximately 160C. Either the power or EN must be recycled to clear the latch. Band Gap Reference A 0.85% precision Band Gap reference acts as the internal reference voltage standard of the chip, which all critical biasing voltages and currents are derived from. All references to VREF in the equations to follow will assume VREF = 1.7V. Precision DAC This 6-bit digital-to-analog converter (DAC) serves as the programmable reference source of the Core Comparator. Programming is accomplished by logic voltage levels applied to the DAC inputs. The VID code vs. the DAC output is shown in the following table. The accuracy of the VID /DAC is maintained on the same level as the Band Gap reference.
5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VDAC V 1.708 1.692 1.676 1.660 1.644 1.628 1.612 1.596 1.580 1.564 1.548 1.532 1.516 1.500 1.484 1.468 1.452 1.436 1.420 1.404 1.388 1.372 1.356 1.340 1.324 1.308 1.292 1.276 1.260 1.244 1.228 1.212 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VDAC V 1.196 1.180 1.164 1.148 1.132 1.116 1.100 1.084 1.068 1.052 1.036 1.020 1.004 0.988 0.972 0.956 0.940 0.924 0.908 0.892 0.876 0.860 0.844 0.828 0.812 0.796 0.780 0.764 0.748 0.732 0.716 0.700
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SC453
POWER MANAGEMENT Applications Information (Cont.)
CORE CONVERTER CONTROLLER Core Comparator This is an ultra-fast hysteretic comparator with a typical propagation delay of about 20ns at a 20mV overdrive. Hysteresis is generated by the current set at the HYS pin impressed upon an external resistor connected to the CMP pin. Current Limit Comparator The Current Limit Comparator monitors the core converter output current and turns off the high side FETs when the current exceeds the upper current limit threshold, VHCL and is re-enabled only if the phase current drops below the lower current limit threshold, VLCL. The current is sensed by monitoring the voltage drop across the current sense resistor, RCS connected in series with the core converter inductor. VHCL and VLCL are fixed by the current set at the HYS pin impressed upon an external resistor connected to the CLRF pin. Current Limit Latch If the CORE voltage goes lower than 14% below the VID (i.e., out of the power good window), then sustained current limiting (32 current limit pulses) will cause the part to permanently latch off. The latch is inhibited during softstart. Core Converter Soft-Start Timer This block controls the start-up ramp time of the CORE voltage up to the boot voltage. The primary purpose is to reduce the initial in-rush current on the core input voltage (battery) rail. Cycle-by-Cycle Power-Save A zero crossing comparator detects when the currents through the external sense resistor reduces to zero. When the current in the external sense resistor reaches zero, the bottom FET is latched off. The latch is reset when the controller decides to switch on the top FET. This prevents excessive switching at light loads and hence saves switching power losses. DAC Slew Control The output of the DAC will slew at a rate defined by the current in the SS pin and the capacitor applied externally to the SS pin. The slew rate (charge current) applied depends on which mode (soft-start, VID or sleep transition) is in effect. The SS capacitor together with the DAC capacitor will determine the stability of the DAC, a 1nF capacitor is recommended for the DAC pin. Blanking During VID Changes On any VID change or Sleep change, the PG# and PG_ DEL signals are blanked for 62 switching cycles to prevent glitching during the transition. Sleep Function In sleep mode, the DAC output is set by the voltage on the SLPV pin when the SLP pin is held high. In "VID Sleep" mode, the DAC output is set by the VID bits when SLP is held high. During sleep, the hysteresis and current limit hysteresis currents are reduced to 70% of their nominal values. SLPV/VID Sleep Mode By default, the controller is in "SLPV controlled Sleep" mode. In this mode, the voltage applied to the SLPV pin appears at the DAC output when SLP is asserted. By holding the SLPV pin at VCCA during start-up, "VID controlled sleep" mode is engaged. In this mode, the DAC output continues to be set by the VID inputs even when SLP is asserted.
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SC453
POWER MANAGEMENT Applications Information (Cont.)
PG# Output This is an open-drain output and should be pulled up externally. This signal is asserted (pulled low) by the SC453 whenever the core voltage is within 14% of the VID programmed value. If the chip is disabled or enabled in UVLO, then PG# is de-asserted. During start-up PG# remains de-asserted until the core voltage has reached the defined boot voltage and remains there for the BOOT period (10S minimum). This signal is forced low (asserted) during VID and sleep transitions. PG_DEL Output This signal is delayed a minimum of 3mS from first assertion of the PG# signal. This is an open drain output and should be pulled up externally. This signal is asserted (open drain) by the SC453 whenever the core is within 14% of the VID programmed value. If the chip is disabled or enabled in UVLO, then PG_DEL is de-asserted. The signal is forced high (open drain) during VID and sleep transitions. Start-Up and Sequencing On start-up, VCORE ramps to the boot voltage set by the BOOTV pin irrespective of the status of the VID pins. After a minimum of 10s, PG# asserts, and VCORE responds to the VID inputs. The controller will then count 1007 switching cycles before asserting PG_DEL.
Summary of Fault Conditions
Protection Mode
Supply UVLO (VCCA, V5) 32 Cycle Current Limit 114% VCORE OVP 2.0VCORE OVP Thermal Shutdown
Latched?
No Yes Yes Yes Yes
When Active
Always SS has terminated and PGDEL is low SS has terminated and PGDEL is low Always Always
Driver Status
All low TG low BG high BG high BG, TG low
SS Pin Status
Low Sawtooth High High High
Driver Timing Diagram
CMPRF
REFIN
CMP
tpdlTG tfTG
tpdhTG
(4)
tr TG
TG
tpdhBG
(4)
trBG
tpdl BG
tfBG
tspd
BG
Note (4): subtract a typical value of 17ns for the core comparator delay since this parameter is specified from a CMP edge.
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SC453
POWER MANAGEMENT Applications Information (Cont.)
DESIGN PROCEDURE Step 1: Define Constants
VINMAX := 20V VINMIN := 8V IMAX_FL := 20A
Maximum input voltage Minimum input voltage Maximum load current, highest output voltage Leakage current, highest output voltage The highest VCORE voltage The lowest VCORE voltage SC453 Internal reference voltage Output capacitance per cap ESR per cap Current sense resistor Parasitic resistance from the current sense resistor to the processor Voltage droop allowed for a low current to high current transient Voltage rise allowed for a high current to low current transient Desired maximum output ripple
Step 2: Output Inductor and Capacitor Selection The SC453 has "passive" droop. The voltage at full load is less than the DAC voltage by the voltage drop across the current sense resistor and any PCB copper losses from the sense resistor to the processor socket. The steadystate voltage at full load is:
VMAX_FL := VMAX_NL - RCS + RCU IMAX_FL VMAX_FL = 1.182 V
(
)
ILKGMAX := 5A VMAX_NL := 1.212V VMIN_NL := 0.956 V VREF := 1.7V C OUT := 330 F RESR := 6m RCS := 1m RCU := 0.5m
Output capacitance and ESR values are a function of transient requirements and output inductor value. Figure 1 illustrates the response of a hysteretic converter to a positive transient. In a hysteretic converter with passive droop, like the SC453, two conditions determine if you meet the positive transient requirements. A.
ESR VPOS_TRANS
(IMAX_FL - ILKGMAX) ( )
B.
VNEG_TRANS deltaV C OUT
VPOS_TRANS := 50mV VNEG_TRANS := 50mV VRIPPLE := 20m V
Figure 1 - Hysteretic Converter Response to a Positive Transient The first condition is easy to see; if the ESR is too high, the transient response will fail.
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SC453
POWER MANAGEMENT Applications Information (Cont.)
In the second condition, because the hysteretic converter responds in < 100ns, the capacitor does not droop very far before the inductor current starts ramping up. (This is not true of control schemes where time constants in the error amplifier cause delays.) Once the inductor current starts to rise, the increasing V of the capacitor is offset by reduced V from the ESR, so V is constant. If the V due to the charge taken from the capacitor before the inductor current reaches the load current (note the shaded area on the graph) is less than VPOS_TRANS, then the transient response passes. Since the highest output voltage has the most severe requirements, any other modes are satisfied by a design optimized for the highest output voltage. C.
ESRMAX :=
Based on the following four factors: 1) minimum inductance requirement; 2) device availability at the time we designed the evaluation board; 3) low DCR ; 4) height and package size consideration. Keep in mind, the choice you make should be based upon the requirement of the converter design, including minimum inductance, minimum saturation current, efficiency, foot area, maximum allowable height, and of course, device availability. In the current demo board design, G.
L1 := 0.60 H
(IMAX_FL - ILKGMAX)
-3
VPOS_TRANS
This value of inductance is required up to maximum load. Inductors with a "swinging choke" characteristic, where the zero current value of inductance is much less than the full load current inductance can be used, as long as the above restriction is met. Then, the worst-case (low input voltage) response time (the time for the current to reach the new transient value) is:
L1 IMAX_FL - ILKGMAX VINMIN - VMAX_NL dT = 1.326 x 10
-6
ESRMAX = 3.333 x 10
dT :=
(
)
For the second condition, we need to know the inductor value, which is a function of the highest desired switching frequency. The maximum frequency occurs at the highest input voltage. As a reasonable compromise between efficiency and component size, a maximum switching frequency of 350kHz is desired. D. E.
F S := 350K Hz VMAX_NL VINMAX
H.
s
Add ~100ns for the propagation delay from a change at the output to the MOSFET switch turning on in reaction. Since the shaded area is triangular, the total charge taken out of the capacitor = (dI / dt) / 2. Q = C / dV = (dI / dt) / 2, therefore;
dMIN :=
I.
C MINP :=
(IMAX_FL - ILKGMAX) (dT + 1 10 - 7 sec)
VPOS_TRANS
-4
F.
LMIN := dMIN
(VINMAX - VMAX_NL) (ESRMAX + RCS)
F S VRIPPLE
ESRMAX + RCS
H ESRMAX
C MINP = 4.278 x 10
F
LMIN = 5.422 x 10
-7
This condition applies only to the positive transient.
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SC453
POWER MANAGEMENT Applications Information (Cont.)
LOAD RELEASE The worst-case for the transient load release to happen is when the hysteresis has just reached the maximum, (i.e., the high-side switch has just turned of); at this time the inductor has reached its peak current.
IRIPPLE := t := 0 , 10n s .. 10 s
(VINMAX - VMAX_FL) dMIN
L1 F S
IL( t) := It0 -

VMAX_FL t L1
L1 LMIN
ICAP( t) := IL( t) - ILKGMAX
IRIPPLE = 6.01 A IRIPPLE 2
It0 := IMAX_FL + It0 = 23.005 A
Since the output inductor is discharging at a fixed rate, there are two terms contributing to the increase of the voltage on the output capacitors: 1) is due to the ESR of the output capacitor; 2) is due to the added charge contributed by the inductor current. J.
VESR t , N CAP := ICAP( t)
Load is stepping from high to low.
L Rds_ON RDS RCU
(
)
RESR N CAP
K.
dVCAP t , N CAP :=
(
)
ICAP( t) t C OUT N CAP
BG ESR_eq
IMAX IMIN R_LOAD
L.
VTOTAL t , N CAP := VESR t , N CAP + dVCAP t , N CAP
(
)
(
)
(
)
Cout_eq
Rcu_rt
Immediately after the load steps down from IMAX to IMIN, the high side FET is turned off, and the bottom FET is turned on after the dead time. We assume for the worst-case condition, at t = 0, the output inductor is sitting at its maximum; after t = 0, the inductor discharges at a rate equal to VFL / L. (without the consideration of the secondary order effect, such as, Rds_on drop, current sense resistor and copper losses). The energy released from the output inductor during load step-down, charges the output capacitors and is dissipated through the following means: Rds_on, Rcs, Rcu, Rcu_rt, ESR of the output capacitors and load.
The chart above shows the system response for the capacitors defined in Step 1 and the chart to follow shows the details of the response for the chosen number of output capactors.
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SC453
POWER MANAGEMENT Applications Information (Cont.)
VHYS is created by a current source, IHYS, through R9 (see the diagram below). The current source value is controlled via RHYS. For simplicity it is easier to select a value for R7 (the resistor in series with the CMP pin) first, and then calculate RHYS, as follows: N.
R7 := 1K RHYS := 2 VREF
.
VHYS R7
RHYS = 102.0 K
Step 3: Setting RHYS The next step is to calculate RHYS. Since the SC453 is a hysteretic controller, it regulates the amount of output ripple according to a hysteresis value set by RHYS. The designer must therefore decide upon the amount of desired output ripple, and then set RHYS accordingly. The hysteresis controls the amount of ripple at the point of regulation, which is the point between the inductor and the current sense resistor. The amount of ripple at the output is defined by the current sense resistor and the output cap, ESR. This factor is taken into account in the equation shown below relating VRIPPLE to VHYS. To achieve tight accuracy, it is recommended that the output ripple be set to 20mV peak-to-peak.
In the SC453 application circuit, RHYS consists of three resistors (R3, R4 and R5). These resistors also form the dividers for BOOTV and SLPV. Note also that depending on circuit layout and parasitics, RHYS may have to be adjusted slightly to obtain optimum performance. (We will come back to calculate the above resistors after we set the PBOOT and Deeper Sleep voltages). To increase hysteresis without having to change the divider resistors, a fourth resistor (R14), can be added. Additional hysteresis is needed when inductances in the current sense paths cause additional signal that add to the resistive signal, limiting the accuracy of the calculations.
SC453
HYS R14 R5 BOOTV R4
ESR :=
RESR N CAP
ESR = 1.5 x 10
-3
VRIPPLE = 0.02 V
SLPV
M.
VHYS := VRIPPLE VHYS = 0.033 V
(RCS + ESR)
ESR
R3
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SC453
POWER MANAGEMENT Applications Information (Cont.)
Step 4: BOOTV Design The boot-up voltage for VCORE is set at 1.2V. For the SC453 typical application circuit, R3, R4, and R5 form a voltage divider off VREF and are used to set the boot voltage. For simplicity, we define RBOOT : = R3 + R4.
VBOOT := 1.2V RHYS := 1 1 R25 + 1 RBOOT + R5 R3 := ( 1 0 0 ) soln R4 := ( 0 1 0 ) soln R5 := ( 0 0 1 ) soln soln := lsolve M x , v
R14 RHYS R14 - RHYS v := 0 0

O.
(
)
5.011 x 10 4 soln = 3.007 x 10 4 4 3.341 x 10
R3 = 5.011 x 10 R4 = 3.007 x 10 R5 = 3.341 x 10
4 4 4
P.
RBOOT := VBOOT R5 VREF - VBOOT
Step 5: Sleep Voltage Design The sleep voltage is set at 0.750V nominally using the R3 - R4 - R5 divider. Q.
VSLP := 0.750V R3 := VSLP
From the standard 1% resistor value table, we choose the following values according to the calculation results: R5 = 33.2K. R4 = 30.1K R3 = 49.9K Step 6: Current Limit Calculation Setting the threshold for current limit is a relatively straightforward process. To do this we must calculate the peak current based on the maximum DC value plus the worst-case ripple current. The following calculations apply for a single phase. Worst-case ripple occurs at the highest input voltage. Since ripple is also inversely proportional to inductance, it is recommended that the minimum inductance value be used based on the manufacturer's specified tolerance:
LLOW := L1 ( 1 - 20%) LLOW = 4.8 x 10
-7
(R4 + R5)
VREF - VSLP
R3, R4 and R5 are calculated using a matrix to solve the simultaneous equations. R14 is set at 1M as a placeholder:
R14 := 1000 K
1 1 1 VBOOT - 1 1 VREF - VBOOT M x := -1 -1 VSLP 1 VSLP V VREF - VSLP REF - VSLP

R.
IRIPPLE_MAX :=
H
(VINMAX - VMAX_NL) dMIN
LLOW F S
IRIPPLE_MAX = 6.777 A
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SC453
POWER MANAGEMENT Applications Information (Cont.)
To calculate the maximum DC value of current we must add the maximum DC current and the maximum ripple value to obtain peak current: S.
IPEAK := IMAX_FL + IRIPPLE_MAX 2
We set the current limit at ICLIM = ICLMAX, and then solve for RCL, which is R6 in the typical applications circuit. For balance, R8, in series with the CLRF pin is kept the same value as R6. V.
RCL := ICLIM RHYS RCS 2.5 VREF R6 := 681 R8 = 681
IPEAK = 23.389 A
It is recommended that the current limit be set at 120% of the peak value to allow for inductor current overshoot during load transients: T.
ICLIM := 120% IPEAK ICLIM = 28.066 A
RCL = 673.59 R8 := R6
The Current Limit Comparator internal to the SC453 monitors the output current and turns the high side switch off when the current exceeds the upper current limit threshold, ICLMAX and re-enables only if the load current drops below the lower current limit threshold, ICLMIN. The current is sensed by monitoring the voltage drop across the current sense resistor RCS. Current limiting will cycle from ICLMAX to ICLMIN for 32 switching cycles to allow for short term transients, then the converter is latched off. ICLMAX and ICLMIN are set according to the following equations: U.
ICLMAX := 3 VREF RCL RHYS RCS
Step 7: Small Capacitors/Resistor Selection Several small capacitors are required for signal filtering. Use SMT ceramic capacitors with an X7R or better temperature coefficient. COG is preferred. C11, which filters the output voltage feedback, is sized to provide filtering beyond the 5th harmonic of the fundamental.
C11 := 1 2 R7 F S 5
- 11
W.
C11 = 9.095 x 10
F
ICLMIN := 2 VREF
RCL RHYS RCS
In the evaluation board design, we use 100pF, 603, X7R ceramic caps for C11. The DAC output requires a 1nF, X7R or COG capacitor (C23) for high frequency noise filtering. The values for C12 and C13 are calculated in a similar manner, though they are returned to the CORE pin because that is the reference point for the current limit comparator. X.
C 12 := 1 2 R6 F S 5
- 10
C 13 := C 12 C 13 = 1.335 x 10
- 10
C 12 = 1.335 x 10
F
F
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SC453
POWER MANAGEMENT Applications Information (Cont.)
Step 8: Calculate Input RMS Current In order to calculate the worst-case input RMS current, we need to assume the efficiency at VIN_MIN and full load. From the measurement result, we are safe to assume 80%, (this number is very conservative, actual efficiency should be much higher). The actual converter efficiency depends on component selection, layout, airflow, etc.
POUT := IMAX_FL VMAX_FL POUT = 23.64 W dVin := 250mV DMAX := 0.5 Tin := 1 FS IPEAK 2 DMAX - DMAX
-5 2 Tin
C IN_MIN :=
dVin
C IN_MIN = 3.341 x 10 C IN := 10F
F
PIN :=
POUT 85% PIN VINMIN VMAX_FL VINMIN
N IN_MIN_RIPPLE := ceil IIN_DC = 3.476 A
CIN_MIN
C IN
IIN_DC :=
D :=
N IN_MIN_RIPPLE = 4
IRMS :=
2 2 (IMAX_FL) - IIN_DC D + IIN_DC ( 1 - D)
Based on the above calculations, we choose N = 4 for the input capacitor. Step 9: OVP No calculations are necessary for Over-Voltage Protection. If VCORE is greater than +14% of the DAC (i.e., out of the power good window), the SC453 will latch off and hold the low-side driver on permanently (for each phase). Either the power or EN must be recycled to clear the latch. The latch is disabled during soft-start and VID/DeeperSleep transitions. The latch is enabled if VCORE exceeds 2V even during VID/DeeperSleep transitions to ensure that the processor maximum is not exceeded. The table on Page 13 is a summary of fault conditions using SC453. Step 10: Soft-Start/DAC Slew Control The soft-start cap C21 in the SC453 design serves three conditions: 1) to define the soft-start ramp; 2) to define the DAC slew rate during sleep and VID transitions (during VID transitions the SS current is nominally +/- 120A. During sleep transitions the SS current increases to +/240A); 3) during start-up, the SS current is normally +/6.5A. We will be doing three soft-start exercises based on the above three conditions for SC453 application:
IRMS = 7.116 A C I_RMS := 2A
10F@25V, MLCC cap from Panasonic is rated 2A RMS.
C I_NUM := ceil
IRMS CI_RMS
C I_NUM = 4
The calculation indicates four of these MLCC caps satisfy the worst-case RMS current requirement. Input Capacitance Calculation: (based on ripple voltage) dVin is the allowable input ripple voltage contributed by the amount of input capacitance. For this exercise, we use 250mV as the allowable input ripple voltage. The maximum value occurs at D = 0.5
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SC453
POWER MANAGEMENT Applications Information (Cont.)
1. Start-Up:
ISS := 6.5 A dtSU := 3 m s dVdacSU := VMAX_NL C SS_max_startup := ISS dtSU dVdacSU
-8
C SS_max_startup = 1.609 x 10
F
2. VID Change:
ISSV := 120 A dtV := 100 s dVdacV := VMAX_NL - VMIN_NL C SS_max_VID := ISSV dtV dVdacV
-8
C SS_max_VID = 4.687 x 10
F
3. Sleep Entry/Exit:
ISSS := 240 A dtS := 33 s dVdacS := VMAX_NL - VSLP C SS_max_drs := ISSS dtS dVdacS
-8
C SS_max_drs = 1.714 x 10
F
Exercise #1 predicts the max capacitance allowed. In order to allow tolerance, we choose C22 = 15nF.
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SC453
POWER MANAGEMENT
Outline Drawing - TSSOP-28
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 e/2 B D A2 A C bxN bbb A1 C A-B D E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.002 .031 .007 .003 .378 .169 .382 .173 .252 BSC .026 BSC .018 .024 (.039) 28 0 .004 .004 .008 .047 .006 .042 .012 .007 .386 .177 0.05 0.80 0.19 0.09 9.60 4.30 9.70 4.40 6.40 BSC 0.65 BSC 0.45 0.60 (1.0) 28 0 0.10 0.10 0.20 1.20 0.15 1.05 0.30 0.20 9.80 4.50
.030
0.75
8
8
aaa C SEATING PLANE
H GAGE PLANE 0.25 (L1) L c
01
SIDE VIEW
SEE DETAIL
A
DETAIL
A
NOTES: 1. 2. 3. 4. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MO-153, VARIATION AE.
Marking Information
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SC453
POWER MANAGEMENT Land Pattern - TSSOP-28
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
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